1. Field of the Invention
The present invention relates generally to a compound semiconductor field effect transistor. More specifically, the invention relates to a compound semiconductor field effect transistor having a gate electrode formed in a recess portion.
2. Description of the Related Art
A compound semiconductor, typically GaAs, is characterized in higher electron mobility and lower noise in comparison with Si. Therefore, in the application for performing high speed and high frequency amplification with low noise, transistors employing the compound semiconductor have been frequently used. In such case, it is typical to use the compound semiconductor as MESFETs having Schottky gates for effectively utilizing high mobility property thereof. On the other hand, in case of a transistor for large output, a recess structure is employed for elevating a breakdown voltage by reducing concentration of electric field to a drain of the gate without increasing source resistance Rs.
FIG. 1 is a section showing the conventional GaAs field effect transistor (MESFET) for large output having a recess structure (hereinafter, this prior art will be referred to as "first prior art"). In FIG. 1, 1 denotes a semi-insulative GaAs substrate formed with an undoped GaAs buffer layer (not shown) on the surface. On the substrate, an n-type GaAs layer 2 serving as channel layer is formed. 0n the surface of the n-type GaAs layer 2, an n.sup.+ type GaAs layer 4 is formed for ohmic contact with a source/drain electrode. In the n.sup.+ -type GaAs layer 4 and the n-type GaAs layer 2, a recess portion 20 is formed by removing the entire depth of the n.sup.+ -type GaAs layer 4 and in the partial depth of the n-type GaAs layer 2 by etching, in a width greater than a predetermined gate region. At the center of the recess portion 20, a gate electrode 7 in Schottky contact with the n-type GaAs layer 2 is formed. On the other hand, on the n.sup.+ -type GaAs layer 4, a source electrode 8 and a drain electrode 9 are formed.
It should be noted that this type of the power MESFET has been known in IEEE Transactions on Electron Devices, Vol ED-25, No. 6, pp 563-567, "Improvement of the Drain Breakdown Voltage of GaAs Power MESFET's by a Simple Recess Structure", for example.
This first prior art has a problem in that a transistor characteristic may be degraded by applying a power at high temperature. FIG. 2 is a graph showing variation of a drain current when the transistor of FIG. 1 is formed to have a gate length of 1 .mu.m and a gate width of 5 mm, and 12 V drain voltage is applied with maintaining a temperature at 250.degree. C., as high temperature burn-in test. As can be seen a drain current is gradually lowered after about 500 hours. This degradation of the characteristics is considered to be caused by occurrence of crystal dislocation in the drain side end of the recess and by propagation of the dislocation due to continuing of application of power under high temperature.
After forming the shown MESFET, a protective layer is formed. Then, the MESFET is assembled in a package. Since the MESFET has different thermal expansion coefficient to the protective layer and the semiconductor crystal of the package or so forth, a stress is created within a crystal. For example, when the FET is mounted on a Cu package, since Cu has greater thermal expansion coefficient than GaAs, compression stress is exerted on the GaAs as cooled after mounting. Then, the stress resided within the crystal concentrates at the corner portion of the recess. Also, at the drain side end of the recess, concentration of the electric field is caused to concentrate the current at this portion. Therefore, when high voltage is applied to the drain as in the high temperature burn-in test, significant electric field concentration and high current concentration is caused at the drain side end of the recess to make the corresponding portion high temperature, locally. Then, by the stress as set forth above and concentration of the electric field and the current, crystal dislocation is caused at the end portion of the recess. When application of power is maintained, the defect thus caused extends to a channel region. As a result, degradation of the transistor characteristics is caused.
On the other hand, Japanese Unexamined Patent Publication (Kokai) No. Heisei 4-280640 proposes to provide a InGaAs layer serving as an etching stopper below a contact layer (hereinafter, this prior art will be referred to as "second prior art"). It should be noted that the semiconductor disclosed in the above-identified publication is not directed to a power transistor. FIG. 3 shows a section showing a structure of a transistor proposed in the above-identified publication. The shown transistor is fabricated through the following process.
On a semi-insulative GaAs substrate 11, an undoped GaAs layer 12 as a channel layer, n-type AlGaAs layer 13 as a carrier supply layer, an undoped GaAs layer 14 as a cap layer of a gate metal, InGaAs layer 15 as an etching stop layer and n.sup.+ -type GaAs layer 16 as a contact layer are grown in order. On the n.sup.+ -type GaAs layer 16, a source electrode 18 and a drain electrode 19 are formed. Thereafter, the n.sup.+ -type GaAs layer 16 and InGaAs layer 15 in the region where a gate electrode should be formed, are removed. Then, the removed portion, the gate electrode 17 is formed.
However, as set out later, in comparison with GaAs, InGaAs is not easily cause crystal dislocation and the propagation speed of the dislocation is low. Therefore, even when a means for forming the InGaAs layer on the upper portion of the recess is applied to the power MESFET, as disclosed in the second prior art, crystal dislocation is started from GaAs and thus, dislocation occurrence suppressing effect cannot be expected. Furthermore, since a stress at the hetero interface of GaAs/InGaAs is added, spreading of dislocation is rather promoted.